1. Field of the Invention
The present invention relates to production methods for a compound semiconductor device. In particular, it relates to production methods for a MESFET (a Schottky's FET) including a self-aligned process.
2. Related Background Art
A production method for a MESFET in which a compound semiconductor is used as a material, for example, is described in U.S. Pat. No. 4,636,822. In this document, MESFET having an LDD (lightly doped drain) structure is disclosed as shown in FIGS. 1A to 1C, FIGS. 2A to 2C and FIGS. 3A and 3B. Its production method is explained hereinafter.
For example, on a compound semiconductor substrate 101 composed of semi-insulated GaAs(gallium arsenide), an insulated layer(silicon nitride layer) 102 to separate the element, such as SiN (silicon nitride) layer or the like, is formed (FIG. 1A), and a first resist pattern 130 having an opening at an element region is formed on the insulated layer 102 (FIG. 1B). Next, a part of the insulated layer 102 corresponding to the opening of the first resist pattern 130 is etched by RIE (reactive ion etching), and ion implantation is performed to form a channel layer 120 (FIG. 1C).
Next, after removing the first resist pattern 130 a second resist pattern 131 with an opening only at a portion, where a gate electrode is formed, is formed on the substrate 101 and the insulated layer 102. And thereafter, a gate electrode material 113 is uniformly evaporated or vapor-deposited on the substrate 101 exposed by the opening and the second resist pattern 131 (FIG. 2A). As the gate electrode material 113, it is exemplified by metals having a high melting point such as, for example, W(tungsten), Mo(molybdenum), and Ti(titanium) and silicides thereof.
Next, the second resist pattern 131 to form a gate electrode is removed, simultaneously the gate electrode material 113 at unnecessary portions is also subjected to lift-off (FIG. 2B). Incidentally, the gate electrode 113 is formed by means of the lift-off method as an example, however, it is also possible to form it by an etching method.
Next, an insulated material for forming the first side wall of the gate electrode 113 (for example, SiO.sub.2 (silicon dioxide) or the like) is deposited on the whole surface of the substrate 101, and shaped in the form of the first side wall 104 by anisotropic etching, reminding the insulated material on the side face of the gate electrode 113. Using the gate electrode 113, the first side wall 104 and the insulated layer 102 as masks, a lightly doped layer 121 is formed by ion implantation with self-alignment (FIG. 2C). Furthermore, an insulated material for forming the second side wall of the gate electrode 113 (for example, SiO.sub.2 or the like) is deposited on the whole surface, and shaped again in the form of the second side wall 105 by anisotropic etching, reminding the insulated material on the side face of the first side wall. Then, using the gate electrode 113, the first side wall 104, the second side wall 105 and the insulated layer 102 as marks, a heavily doped layer 122 is formed by performing ion implantation with self-alignment (FIG. 3A). Thereafter, in accordance with an ordinary process, ohmic electrodes, namely source electrode 108 and a drain electrode 107 are formed, and MESFET having a LDD structure is completed (FIG. 3B).
In the above-mentioned method, shaping processing of the first side wall 104 and the second side wall 105 is performed by anisotropic etching of SiO.sub.2 with RIE. However, in this case, the shape of each side wall is greatly affected by the quality or thickness of the layer of the insulated material forming the side wall, as well as dispersion in etching caused by RIE, and it has been difficult to obtain the same shape with good reproducibility. When the shape of the side wall changes, the shapes of the lightly doped layer 121 and the heavily doped layer 122, forming by the ion implantation using the side wall as a mask change. Therefore, the resultant characteristics of FET greatly change, and it has been an obstacle to obtaining high integration and high yield. Especially in the case of the above-mentioned example, the shaping processing for the side wall has to be performed twice, and this problem has been all the more serious.
Furthermore, there is another problem, in that because anisotropic etching of SiO.sub.2 with RIE is used during shaping processing for the first side wall 104 and the second side wall 105, the surface of the semi-insulated compound semiconductor substrate 101, which is exposed at that time, could be damaged by etching. This damage due to etching caused deterioration in characteristics such as in the conductance of FET and reduction in break-down voltage. Especially in the case of the above-mentioned example, the shaping processing for the side wall is performed twice, and this problem is all the more serious.